? semiconductor components industries, llc, 2006 august, 2006 ? rev. 4 1 publication order number: ntd78n03r/d ntd78n03r power mosfet 25 v, 85 a, single n ? channel, dpak features ? low r ds(on) to minimize conduction losses ? optimized gate charge to minimize switching losses ? pb ? free packages are available applications ? vcore applications ? dc ? dc converters ? optimized for low side switching maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 25 v gate ? to ? source voltage v gs 20 v continuous drain current (r ja ) (note 1) steady state t a = 25 c i d 14.7 a t a = 85 c 11.4 power dissipation (r ja ) (note 1) t a = 25 c p d 2.3 w continuous drain current (r ja ) (note 2) t a = 25 c i d 11.3 a t a = 85 c 8.8 power dissipation (r ja ) (note 2) t a = 25 c p d 1.4 w continuous drain current (r jc ) t c = 25 c i d 85 a t c = 85 c 66 power dissipation (r jc ) t c = 25 c p d 76.9 w pulsed drain current t p = 10 s i dm 98 a current limited by package t a = 25 c i dmaxpkg 32 a operating junction and storage temperature t j , t stg ? 55 to 175 c source current (body diode) i s 77 a drain to source dv/dt dv/dt 8.0 v/ns single pulse drain ? to ? source avalanche energy (v dd = 24 v, v gs = 10 v, l = 5.0 mh, i l (pk) = 5.5 a, r g = 25 ) e as 75 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. surface ? mounted on fr4 board using 1 in sq pad size, 1 oz cu. 2. surface ? mounted on fr4 board using the minimum recommended pad size. case 369c dpak (bend lead) style 2 marking diagrams & pin assignments y = year ww = work week 78n03r= device code g = pb ? free package 3 source 2 drain 4 drain 1 gate 3 source 2 drain 4 drain case 369d dpak (straight lead) style 2 1 gate yww 78 n03rg yww 78 n03rg 25 v 5.0 @ 11.5 v r ds(on) typ 85 a i d max v (br)dss 7.5 @ 4.5 v http://onsemi.com 1 2 3 4 see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information 1 2 3 4 case 369ac 3 ipak (straight lead) 1 2 3 4 n ? channel d s g
ntd78n03r http://onsemi.com 2 thermal resistance maximum ratings parameter symbol value unit junction ? to ? case (drain) r jc 1.95 c/w junction ? to ? ambient ? steady state (note 3) r ja 65 junction ? to ? ambient ? steady state (note 4) r ja 110 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 25 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 10 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 20 v t j = 25 c 1.5 a t j = 125 c 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.0 1.7 3.0 v negative threshold temperature coefficient v gs(th) /t j ? 5.3 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10v to 11.5 v i d = 30 a 5.0 5.8 m i d = 15 a 4.9 5.7 v gs = 4.5 v i d = 30 a 7.5 9.0 i d = 15 a 7.2 8.5 forward transconductance gfs v ds = 15 v, i d = 10 a 23 s charges, capacitances and gate resistance input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 12 v 1794 pf output capacitance c oss 882 reverse transfer capacitance c rss 373 total gate charge q g(tot) v gs = 4.5 v, v ds = 20 v, i d = 20 a 19.4 24 nc threshold gate charge q g(th) 0.8 gate ? to ? source charge q gs 2.9 gate ? to ? drain charge q gd 12.4 switching characteristics (note 6) turn ? on delay time t d(on) v gs = 4.5 v, v ds = 20 v, i d = 20 a, r g = 2.5 11 ns rise time t r 75 turn ? off delay time t d(off) 18 fall time t f 17 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 30 a t j = 25 c 0.8 1.0 v reverse recovery time t rr v gs = 0 v, dis/d t = 100 a/ s, i s = 20 a 38 ns charge time ta 16.5 discharge time tb 22 reverse recovery time q rr 31 nc 3. surface ? mounted on fr4 board using 1 in sq pad size, 1 oz cu. 4. surface ? mounted on fr4 board using the minimum recommended pad size. 5. pulse test: pulse width 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures.
ntd78n03r http://onsemi.com 3 20 40 60 80 100 120 2 1.4 1.2 0.8 0.6 1000 10000 100000 0.004 08 6 4 i d , drain current (amps) 0 v gs , gate ? to ? source voltage (v) figure 1. on ? region characteristics figure 2. transfer characteristics i d , drain current (amps) 3 10.25 6.50 5.25 6 4.00 48910 figure 3. on ? resistance versus gate ? to ? source voltage v gs , gate ? to ? source voltage (v) figure 4. on ? resistance versus drain current and gate voltage i d , drain current (a) r ds(on) , drain ? to ? source resistance (m ) figure 5. on ? resistance variation with temperature t j , junction temperature ( c) figure 6. drain ? to ? source leakage current versus voltage v ds , drain ? to ? source voltage (v) i dss , leakage (na) 60 ? 50 100 75 0 ? 25 125 175 03 8 10 0.002 0.01 0.008 218 16 14 20 v ds , drain ? to ? source voltage (v) 20 40 10 v gs = 0 v t j = 100 c t j = 175 c v gs = 4.5 v v gs = 10 v t j = 25 c i d = 30 a t j = 25 c v ds 10 v t j = 25 c t j = ? 55 c t j = 125 c r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance (normalized) t j = 25 c 50 25 45 2 v gs = 4 v 2.4 v 2.6 v 3.5 v 3 v 4.5 v 6 v 9.00 7.75 15 20 25 30 80 100 120 10 v 0 1.6 1 i d = 30 a v gs = 10 v to 11.5v 100 2 1 7 5 150 11.50 0.006 1.8 4681012 19 7 5 3 67
ntd78n03r http://onsemi.com 4 5 10 15 20 25 30 35 40 0.3 0.6 0.9 1.2 10 5 0 5 10152025 v gs v ds 2 5 3 0 1000 c, capacitance (pf) 0 q g , total gate charge (nc) figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage versus total charge v gs , gate ? to ? source voltage (v) figure 9. resistive switching time variation versus gate resistance v sd , source ? to ? drain voltage (v) i s , source current (amps) 3500 gate ? to ? source or drain ? to ? source voltage (v) 500 2000 1 i d = 20 a t j = 25 c q 1 v gs = 0 v t j = 25 c v gs = 0 v t j = 25 c c rss c iss c oss 1500 04812 16 20 q 2 q t figure 10. diode forward voltage versus current r g , gate resistance (ohms) 1 10 100 1000 t, time (ns) 100 t r t d(off) t d(on) t f 10 v ds = 15 v i d = 20 a v gs = 4.5 v 2500 c rss c iss v ds = 0 v v gs v ds v ds , drain ? to ? source voltage (v) 0 8 12 16 20 0 15 20 3000 4 4
ntd78n03r http://onsemi.com 5 ordering information order number package shipping ? ntd78n03r dpak 75 units/rail ntd78n03rg dpak (pb ? free) ntd78n03rt4 dpak 2500 tape & reel ntd78n03rt4g dpak (pb ? free) ntd78n03r ? 1 dpak straight lead 75 units/rail ntd78n03r ? 1g dpak straight lead (pb ? free) ntd78n03r ? 35 dpak straight lead (3.5 0.15 mm) ntd78n03r ? 35g dpak straight lead (3.5 0.15 mm) (pb ? free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntd78n03r http://onsemi.com 6 package dimensions dpak case 369c ? 01 issue o 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h ? t ? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.180 0.215 4.57 5.45 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4
ntd78n03r http://onsemi.com 7 package dimensions dpak case 369d ? 01 issue b style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k ? t ? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ???
ntd78n03r http://onsemi.com 8 package dimensions 3 ipak, straight lead case 369ac ? 01 issue o d a k b r v f g 3 pl e c j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.043 0.94 1.09 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.134 0.142 3.40 3.60 r 0.180 0.215 4.57 5.46 v 0.035 0.050 0.89 1.27 w 0.000 0.010 0.000 0.25 notes: 1.. dimensioning and tolerancing per ansi y14.5m, 1982. 2.. controlling dimension: inch. 3. seating plane is on top of dambar position. 4. dimension a does not include dambar position or mold gate. w seating plane 0.13 (0.005) w on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ntd78n03r/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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